1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device of a folded bit-line architecture.
2. Description of the Background Art
FIG. 15 is a schematic block diagram showing the configuration of a memory cell array and its peripheral circuits of a conventional semiconductor memory device of a folded bit-line architecture.
A memory cell array 30 includes a plurality of blocks BK0 to BKn. Each block includes a plurality of pairs of folded bit lines BL and /BL, a plurality of word lines WL, and a plurality of memory cells MC. Each of a plurality of sense amplifiers 100 is connected to two pairs of bit lines BL and /BL.
Referring to FIG. 15, in the semiconductor memory device of the folded bit-line architecture, each sense amplifier 100 is connected to two pairs of bit lines BL and /BL. Consequently, the number of sense amplifiers in the semiconductor memory device can be reduced to almost the half of that of a conventional semiconductor memory device.
Reading operation of the semiconductor memory device of FIG. 15 will be described.
In FIG. 15, in the case of selecting block BK1, a plurality of pair of bit lines BL and /BL in the region of selected block BK1 are selected. When attention is paid to a region 301 in FIG. 15, sense amplifier 100 in region 301 selects the pair of bit lines BLL and /BLL on the block BK1 side and disconnects a pair of bit lines BLR and /BLR on the block BK2 side. Each of the other sense amplifiers 100 selects the pair of bit lines BL and /BL on the block BK1 side and disconnects the pairs of bit lines BL and /BL on the block BK2 side and on the block BK0 side.
After selecting the plurality of pairs of bit lines BL and /BL in block BK1 by the operation, a not-shown arbitrary word line WL in block BK1 is selected by a row decoder 40 to thereby select a plurality of memory cells MC (not shown) as targets of the reading operation. The data of selected plural memory cells MC is read out to the corresponding bit line BL or /BL and held by sense amplifier 100 corresponding to the pair of bit lines BL and /BL.
By sequentially changing a column address, the data held by sense amplifier 100 is successively output to not-illustrated data input/output lines IO and IO. A method of successively outputting data of a plurality of memory cells corresponding to a selected word line as described above is called a page mode access.
FIG. 16 is a circuit diagram showing the configuration of region 301 in FIG. 15.
Referring to FIG. 16, sense amplifier 100 is of a flip flop type capable of using an amplified potential as it is for rewriting. Sense amplifier 100 includes P-channel MOS transistors QP1 to QP3 and N-channel MOS transistors QN1 to QN3.
To each of bit lines BLL and /BLL, a plurality of memory cells MC are connected. Between bit lines BLL and /BLL, an equalizer 15 is connected. Equalizer 15 includes N-channel MOS transistors QN4 to QN6. Equalizer 15 operates when an activated equalize signal BLEQL is received by gates of transistors QN4 to QN6 and precharges the potential of the pair of bit lines BLL and /BLL to VCC/2.
Sense amplifier 100 and the pair of bit lines BLL and /BLL are connected to each other via a selection gate SG1. Selection gate SG1 includes N-channel MOS transistors QN7 and QN8. Transistor QN7 is connected between bit line /BLL and a sense node SN1 in sense amplifier 100. Transistor QN8 is connected between bit line BLL and a sense node SN2 in sense amplifier 100. Transistors QN7 and QN8 receive a selection signal SEL by their gates.
To each of bit lines BLR and /BLR, a plurality of memory cells MC are connected. Between bit lines BLR and /BLR, an equalizer 16 is connected. The circuit configuration of equalizer 16 is the same as that of equalizer 15 except that an equalize signal BLEQR is input to the gate of each of transistors in equalizer 16.
Sense amplifier 100 and the pair of bit lines BLR and /BLR are connected to each other via a selection gate SG2. Selection gate SG2 includes N-channel MOS transistors QN9 and QN10. Transistor QN9 is connected between bit line /BLR and sense node SN1 in sense amplifier 100. Transistor QN10 is connected between bit line BLR and sense node SN2 in sense amplifier 100. Transistors QN9 and QN10 receive a selection signal SER by their gates.
The reading operation of the semiconductor memory device having the above-described circuit configuration will be described.
FIG. 17 is a timing chart showing the reading operation in a page mode access of the conventional semiconductor memory device.
Referring to FIG. 17, operation performed in the case where the pair of bit lines BLL and /BLL in FIG. 16 will be described. Before time t0, both equalizer activate signals BLEQL and BLEQR are at the H level, so that both of the pair of bit lines BLL and /BLL and the pair of bit lines BLR and /BLR are precharged to VCC/2.
When block BK1 in FIG. 15 is selected at time t0, out of the two pairs of bit lines connected to sense amplifier 100 in region 301, the pair of bit lines BLL and /BLL is selected. Therefore, selection signal SEL maintains the H level and selection signal SER is rendered to L level. Consequently, transistors QN9 and QN10 in selection gate SG2 are turned off. As a result, the pair of bit lines BLR and /BLR are not selected.
Subsequently, equalizer activate signal BLEQL input to equalizer 15 is rendered to L level at time t1. Consequently, both bit lines /BLL and BLL enter a floating state.
At time t2, word line WLn in FIG. 16 is selected. It is now assumed that, in FIG. 16, a memory cell MC1 connected to word line WLn and bit line /BLL stores L-level data. In this case, the potential on bit line /BLL decreases slightly from VCC/2 at time t2.
When sense amplifier activate signal SEN is rendered to H level and sense amplifier activate signal /SEN is rendered to L level at time t3, sense amplifier 100 starts operating. Specifically, sense amplifier 100 amplifies the potential on bit line /BLL to a ground potential GND and amplifies the potential on bit line BLL to an internal power supply potential VCC.
Sense amplifier 100 amplifies the potential difference between bit lines /BLL and BLL and then maintains the potentials of bit lines /BLL and BLL.
After each of the plurality of sense amplifiers 100 amplifies the potential difference between the corresponding pair of bit lines BLL and /BLL in block BK1, a column address signal output from a column decoder 45 is sequentially changed. A data signal DQi of memory cell MC corresponding to the changed column address is successively output.
As described above, in the page mode access, the sense amplifier amplifies the potential difference between the bit lines of the corresponding pair. After that, until the amplified potential difference is output as data signal DQi, one of the bit lines in the pair is held at internal power supply potential VCC and the other bit line is held at ground potential GND.
At present, a semiconductor memory device is requested to be fabricated finer. By the finer fabrication, interference occurs between an interconnection in a memory cell array of a semiconductor device and a memory cell, and a problem that the charge holding function of the memory cell deteriorates occurs. Particularly, in an SDRAM characterized by a burst output as a kind of the page mode access, a period of holding the potential difference of the bit line pair to be the difference between internal power supply potential VCC and ground potential GND is long in the reading operation. Therefore, when a leak path is included between a bit line and a memory cell due to finer fabrication, deterioration in charge holding capability of the memory cell becomes conspicuous.
FIG. 18 is a schematic diagram for explaining deterioration in charge holding capability of a memory cell in the conventional semiconductor memory device.
Referring to FIG. 18, it is assumed that the charges at storage nodes of memory cells MC10 and MC20 as targets of the reading operation in memory cell array 30 are at the L level. It is also assumed that both memory cells MC1 and MC2 hold H-level data, and both memory cells MC3 and MC4 hold L-level data.
When word line WLn is selected, the potential of a bit line /BLn+1 maintains the L level, and the potential of a bit line BLn+1 maintains the H level. On the other hand, bit line /BLn maintains the L level and bit line BLn maintains the H level.
As a result, a high voltage stress is applied across memory cell MC1 storing the H-level data and bit line /BLn maintained at the L level for a predetermined period. Consequently, if a leak path R1 exists in memory cell MC1, charges dissipate in memory cell MC1. In memory cell MC2 as well, in a manner similar to memory cell MC1, a high voltage stress is applied across memory cell MC2 and bit line /BLn for a predetermined period. Therefore, if a leak path R2 exists in memory cell MC2, charges dissipate in memory cell MC2.
Memory cell MC4 is also similar to memory cell MC1. Since a high voltage stress is applied across memory cell MC4 and bit line BLn, if a leak path R4 exists, charges of memory cell MC4 dissipate.
As a result, in the reading operation in the page mode access, due to application of a high voltage stress to the bit line pair for long time, dissipation of the charges stored in the memory cell occurs.
As the voltage of a semiconductor memory device is being lowered in recent years, there is a tendency that a read margin is narrowed.
FIG. 19A is a schematic diagram for explaining the operation of sense amplifier 100 in the case where L-level data is held in memory cell MC. FIG. 19B is a schematic diagram for explaining the operation of sense amplifier 100 in the case where H-level data is held in memory cell MC.
As shown in FIG. 19A, in the case where data in memory cell MC is at the L level, a bit line to which memory cell MC is connected (hereinbelow, called on the reading side) will be set as bit line/BLa. A bit line to which memory cell MC is not connected (hereinbelow, called a reference side) will be set as bit line BLa. Further, a voltage between the gate and source of transistor QN1 in sense amplifier 100 will be set as Vgsa.
As shown in FIG. 19B, in the case where data in memory cell MC is at the H level, a bit line on the reading side will be set as bit line/BLb. A bit line on the reference side will be set as bit line BLb. Further, a voltage between the gate and source of transistor QN2 in sense amplifier 100 will be set as Vgsb.
FIG. 20 is a timing chart showing the operation of the sense amplifier in the cases of FIGS. 19A and 19B.
Referring to FIG. 20, when data stored in memory cell MC is at the L level as shown in FIG. 19A, bit line /BLa on the reading side is amplified to ground potential GND. Therefore, gate-source potential Vgsa of transistor QN1 before a sensing operation is VCC/2. When sense amplifier 100 starts operating at time t10, at time t12, the potential on reference-side bit line BLa is amplified to internal power supply potential VCC and the potential on reading-side bit line /BLa is amplified to ground potential GND. On the other hand, when data stored in memory cell MC is at the H level as shown in FIG. 19B, the potential on reference-side bit line BLb is amplified to ground potential GND. Therefore, the gate-source potential of transistor QN2 before the sensing operation is equal to VCC/2+xcex94V as the potential of read-side bit line /BLb. xcex94V denotes a potential which is increased when H-level data in memory cell MC is read out to bit line /BLb on the read side. Therefore, gate-source potential Vgsb of transistor QN2 in the case where data stored in memory cell MC is at the H level is higher than gate-source potential Vgsa of transistor QN1 in the case where data in memory cell MC is at the L level. The value of a current flowing by the sensing operation of sense amplifier 100 in the case where the data of memory cell MC is at the H level becomes higher than that of a current flowing by the sensing operation of sense amplifier 100 when the data in memory cell MC is at the L level. As a result, in the case where the data in memory cell MC is at the H level, when sense amplifier 100 starts operating at time t10, read-side bit line BLb is amplified to internal power supply potential VCC and reference-side bit line /BLb is amplified to ground potential GND at time t11 earlier than time t12.
As a result, due to decrease in voltage, the read margin of L-level data becomes narrower than that of H-level data. What is more, the operation of reading L-level data is influenced by ground noise.
FIG. 21 is a schematic diagram for explaining the influence of ground noise exerted on the reading operation.
Referring to FIG. 21, when block BK1 in the memory cell array in the semiconductor memory device is selected and word line WLn is selected, it is assumed that, out of the plurality of memory cells MC1 to MC8 connected to word line WLn, only memory cell MC6 has L-level data, and other memory cells MC have H-level data.
As shown in FIG. 20, the operation of sense amplifier 100 in the case of reading H-level data is faster than the operation of the sense amplifier performed in the case of reading L-level data. In FIG. 21, since a number of sense amplifiers read H-level data, a large discharge current is generated to float ground potential GND. This is ground noise GNDN.
If sense amplifier 100 for reading data stored in memory cell MC7 has not started operation, gate-source potential Vgsa of transistor QN1 in sense amplifier 100 shown in FIG. 19A becomes lower. Further, a case that L-level data is inverted to H-level data may happen.
FIG. 22 is a timing chart showing a case where data is inverted in operation of reading data in memory cell MC6 shown in FIG. 21.
Referring to FIG. 22, the timing chart of the pair of bit lines BLa and /BLa shows the operation of sense amplifier 100 on memory cell MC6. The timing chart of the pair of bit lines BLb and /BLb shows the operation of sense amplifier 100 on memory cell MC other than memory cell MC6. When the reading operation of sense amplifier 100 on the memory cell other than memory cell MC6 starts at time t15, a large charge/discharge current is generated. As a result, ground noise GNDN occurs. In the case where sense amplifier 100 starts reading operation on memory cell MC6 after ground noise GNDN occurs, if ground noise GNDN exerts an influence equally on transistors QN1 and QN2 in sense amplifier 100, there is no problem. However, before the operation of sense amplifier 100, the potential on bit line /BLa on the reading side is lower than that on bit line BLa on the reference side. Therefore, the gate-source potential of transistor QN1 becomes higher than the gate-source potential of transistor QN2. Ground noise GNDN propagates more in reading-side bit line /BLa than reference-side bit line BLa. As a result, although the data stored in memory cell MC6 is at the L level, inversion of the data occurs due to the influence of ground noise GNDN, and there is the possibility that sense amplifier 100 amplifies the potential difference between the pair of bit lines BLa and /BLa by using the data in memory cell MC6 as H-level data.
When gate-source potential Vgs decreases by the influence of ground noise, the sensing operation remarkably deteriorates and a flip flop in the sense amplifier becomes unstable. At this time, if a bit line and a data input/output line are connected to each other, the potential of the bit line is pulled by the potential of the data input/output line. It may cause data destruction.
Although the ground noise has been described above, in addition, influences of variations in charge amount at the time of reading data from a memory cell and variations in sense amplifiers at the time of manufacture cannot be also ignored. Variations in the amount of charges to be read from a memory cell at the time of reading and manufacturing process cause variations in speed of differential amplification. The variations in speed of differential amplification become ground noise or noise between lines, and it deteriorates the operation margin of the sense amplifier.
FIG. 23 is a block diagram showing a part of the memory cell array illustrated in FIG. 15.
Referring to FIG. 23, inter-line capacitance Cb1 exists between bit lines BL and /BL. Between sense nodes SN of sense amplifier 100 as well, inter-line capacitance Csa exists. By inter-line capacitance Cb1 and Csa, noise between lines which occurs due to variations in the amplification speed in the operation of the sense amplifier propagates to bit lines BL and /BL and sense amplifiers 100. As a result, the propagated noise between lines exerts an influence on the operation margin of sense amplifier 100.
For the above reasons, to assure the operation margin of the sense amplifier, the ground noise and noise between lines exerting an influence on the sense operation have to be reduced.
A semiconductor memory device aimed at reducing the noise between bit lines in the reading operation of a sense amplifier of a trap sensing type is reported in Japanese Unexamined Patent Application No. 5-101660. However, since the trap sensing type itself is sensitive to the ground noise and noise between lines, by the trap sensing type, the sensing operation margin deteriorates.
An object of the invention is to provide a semiconductor memory device having a sense amplifier, capable of suppressing deterioration in charge holding capability of a memory cell and preventing erroneous operation.
A semiconductor memory device according to the invention includes first and second bit lines constructing a folded bit-line pair, a memory cell, an equalizer, first and second sense nodes, a sense amplifier, a first switch circuit, a second switch circuit, and a control circuit. The memory cell is connected to the second bit line. The equalizer is connected to the first and second bit lines and precharges the first and second bit lines. The sense amplifier is connected to the first and second sense nodes. The first switch circuit is connected between the first bit line and the first sense node. The second switch circuit is connected between the second bit line and the second sense node. The control circuit controls the equalizer and the first and second switch circuits. The equalizer includes a first potential supply circuit and a second potential supply circuit. The first potential supplying circuit supplies a predetermined potential to the first bit line. The second potential supplying circuit supplies the predetermined potential to the second bit line. During a period between time when the equalizer precharges the first and second bit lines and time when the sense amplifier finishes operation, the control circuit controls the first potential supplying circuit so as to make the first switch circuit off while allowing the second switch circuit remain on, and supply the predetermined potential to the first bit line.
In the semiconductor memory device according to the invention, at the time of reading operation, a bit line on a reference side is disconnected from a sense node and its potential is fixed at VCC/2. In the case of disconnecting the bit line on the reference side from the sense node after the sensing operation, the voltage stress applied across a not-selected memory cell and a bit line can be lessened. Therefore, deterioration in charge holding capability of a memory cell can be prevented.
In the case of disconnecting the bit line on the reference side from the sense node after the sensing operation, in addition to the reduction in voltage address, the bit line on the reference side functions as a shield line for preventing propagation of noise occurring between bit lines. As a result, erroneous operation of a sense amplifier can be prevented. Further, since the charge/discharge current decreases, ground noise can be reduced. As a result, erroneous operation of a sense amplifier can be prevented.
Consequently, a semiconductor memory device having a sense amplifier, which can suppress deterioration in charge holding capability of a memory cell and prevent erroneous operation can be provided.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.